Semiconductor light-emitting devices including light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), vertical cavity laser diodes (VCSELs), and edge emitting lasers are among the most efficient light sources currently available. Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials. Typically, III-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, III-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques. The stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p-type regions.
FIG. 1 illustrates a flip chip LED described in more detail in U.S. Pat. No. 7,256,483. The LED includes n-type layers 16, an active layer 18, and p-type layers 20 grown on a sapphire growth substrate (not shown). Portions of the p-layer 20 and active layer 18 are etched away during the LED forming process, and metal 50 (metallization layer plus bonding metal) contacts the n-layer 16 on the same side as the p-contact metal 24. An underfill material 52 may be deposited in the voids beneath the LED to reduce thermal gradients across the LED, add mechanical strength to the attachment between the LED and the package substrate, and prevent contaminants from contacting the LED material. The n-metal 50 and p-metal 24 are bonded to the pads 22A and 22B, respectively, on a package substrate 12. Contact pads 22A and 22B on package substrate 12 are connected to solderable electrodes 26A and 26B using vias 28A and 28B and/or metal traces. The growth substrate is removed, exposing a surface of n-type layer 16. This surface is roughened for increased light extraction, for example by photo-electrochemical etching using a KOH solution.